`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/22 17:39:35
// Design Name: 
// Module Name: sign_extend
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sign_extend(
    input  logic [15: 0]    data_16bits,
    input  logic [ 1: 0]    ext,
    output logic [31: 0]    data_32bits
    );

    always_comb begin
        data_32bits = 32'b0;
        case(ext)
            2'b00:  begin
                data_32bits = {16'b0,data_16bits};
            end

            2'b01:  begin
                data_32bits = {{16{data_16bits[15]}},data_16bits};
            end

            2'b10:  begin
                data_32bits = {data_16bits,16'b0};
            end
        endcase
    end

endmodule
